[Hiring] RTL EDA Design/Scripting Engineer @ENTERPRISE APPLICATIONS CONSULTING

Role Description

We are seeking a highly skilled EDA Scripting Engineer to join our central methodology and design enablement team. You will design, develop, and maintain automated design flows and methodologies that power our entire ASIC/SoC development process—from RTL to tape-out—using leading-edge EDA tools. This is a critical infrastructure role where you will enable design teams to achieve faster tape-outs, better PPA (Power, Performance, Area), and higher reliability on advanced nodes.

• Design, implement, and optimize end-to-end CAD flows for RTL synthesis, place-and-route, timing closure, power analysis, physical verification, and sign-off.
• Develop and maintain automation scripts (Python, Perl, Tcl) and Makefiles to integrate EDA tools seamlessly across the design pipeline.
• Customize and integrate Process Design Kits (PDKs), libraries, and foundry rules for new process nodes and advanced packaging technologies.
• Troubleshoot flow issues, debug tool integration problems, and provide rapid support to design and verification teams during critical project phases.
• Comfortable with RTL, physical design, verification, and foundry teams to define best-practice methodologies and resolve bottlenecks.
• Evaluate, deploy, and qualify new EDA tool versions, features, and methodologies to improve productivity and quality.
• Implement regression testing, flow validation, and documentation to ensure flow reliability and repeatability.
• Contribute to silicon bring-up learnings and feed back improvements into the CAD infrastructure.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of hands-on experience in CAD flow development or methodology support for ASIC/SoC design.
• Strong proficiency with major EDA tool suites:
• Synthesis: Synopsys Design Compiler / Fusion Compiler or Cadence Genus
• Place & Route: Synopsys ICC2 / Fusion Compiler or Cadence Innovus
• Timing & Power: Synopsys PrimeTime / PrimePower, Cadence Tempus / Voltus
• Physical Verification: Siemens Calibre (DRC/LVS) or Cadence PVS
• Expertise in scripting and automation (Python, Perl, Tcl/Tk, Bash) and Linux/Unix environments.
• Deep understanding of digital design flows, timing analysis, power integrity, and physical verification processes.
• Proven track record of improving design productivity through flow automation and methodology enhancements.
• Excellent problem-solving and debugging skills under tight tape-out schedules.

Preferred Qualifications

• Experience with advanced process nodes (7nm, 5nm, 3nm) and heterogeneous integration (2.5D/3D).
• Familiarity with low-power design flows (UPF/CPF), CDC/RDC checks, and formal verification integration.
• Exposure to cloud-based or distributed CAD environments.
• Knowledge of version control (Git) and CI/CD pipelines for flow development.
• Strong collaboration skills and ability to work with cross-functional teams in a fast-paced environment.

Company Description

This is a remote position.