[Hiring] Analog Design Engineer @Analogue Insight

Role Description

We are seeking a talented and motivated Graduate Analog Design Engineer to join our team and contribute to the design of high-performance serial links and data converters for our chiplet solutions. Working alongside experienced analog designers, you will help design, simulate and verify ADC, DAC, RX, TX and PLL building blocks on advanced FinFET technology nodes, and see your work go into customer silicon. This role is well suited to recent graduates with a strong foundation in analog circuit design who want to learn fast through deep, hands-on work in a small, high-impact team.

Key Responsibilities

• Analog & Mixed-Signal Block Design: Design and optimise sub-blocks of ADC, DAC, RX, TX and PLL circuits (e.g. amplifiers, comparators, bias circuits, references, clock buffers) under the guidance of senior designers.
• Simulation and Validation: Run transistor-level simulations (DC, AC, transient, noise, Monte Carlo and PVT corners) and mixed-signal verification using Cadence, AMS and SystemVerilog to confirm robust performance across operating conditions.
• Performance Optimisation: Learn and apply design techniques to improve key parameters such as gain, bandwidth, linearity, noise, jitter, power consumption and speed.
• Layout Collaboration: Work closely with layout engineers to communicate matching, symmetry and parasitic-sensitive nets, and run post-layout extracted simulations to close the design.
• Modelling & Scripting: Build behavioural models (e.g. Verilog-A) and scripts (e.g. Python, SKILL or OCEAN) to speed up simulation, analysis and design-check flows.
• Silicon Characterization Support: Help prepare test plans and support lab characterisation and debug of silicon as projects progress.
• Design Documentation: Document your designs, simulation results and design-review material clearly, supporting efficient knowledge sharing within the team.
• Technology Awareness: Keep learning about advances in high-speed SerDes, data converters and chiplet interfaces such as UCIe.

Qualifications

• M.S. or Ph.D. in Electrical/Electronic Engineering or a related field, with a focus on analog/mixed-signal circuit design (recent graduates and those graduating within the next 6 months are welcome).
• 0–2 years of industry experience, including internships, placements or research projects.
• Strong grasp of analog fundamentals: CMOS device physics, small-signal analysis, feedback and stability, noise, and mismatch.
• Hands-on circuit design and simulation experience with Cadence Virtuoso/Spectre or similar tools, through coursework, thesis or internship projects.
• Understanding of at least one of: data converters (ADC/DAC), PLLs/clocking, or high-speed TX/RX circuits.
• Excellent analytical and problem-solving skills, with a keen eye for detail.

Requirements

• Thesis, research or internship work on FinFET or other advanced-node technologies.
• A completed tape-out and/or lab measurement experience.
• Familiarity with Verilog/SystemVerilog, Verilog-A or AMS modelling.
• Scripting experience (Python, MATLAB, SKILL or shell) and comfort in a Linux environment.
• Publications or conference contributions in circuits (e.g. ISSCC, VLSI, CICC, ESSCIRC).

Soft & Professional Skills

• Clear, structured communication in professional English—able to explain complex results concisely.
• Collaborative and feedback-oriented mindset, open to learning from design reviews.
• Strong ownership, reliability, and follow-through.
• Curious, self-motivated attitude, eager to learn and explore new tools or methods.
• High level of integrity and professionalism in representing the company and handling sensitive information.

Benefits

• Remote-first flexibility – work from anywhere, with flexible hours.
• Equipment & setup – we’ll provide the tools you need to succeed.
• High-impact projects – design real analog IP used in customer silicon.
• Supportive team culture – a dedicated manager and a team of colleagues ready to help.
• Competitive, transparent compensation – adjusted for your location and engagement model.
• Learning & growth – AI–DLP sessions, technical deep dives, and peer-led knowledge sharing that build both technical depth and system-level perspective.

Recruitment Process

• Founder Call (30 min) – mutual introduction and interest alignment.
• Technical Interview (90 min) – fundamentals, reasoning, and problem-solving.
• Optional: Second Technical Interview (60 min) – another deep-dive into specific topics, which might include a presentation that we'll let you know about in advance.
• HR & Culture Call (45 min) – values, collaboration style, and ways of working.
• Offer & Next Steps – we send the offer and kick off the onboarding process.