[Hiring] Signal and Power Integrity Engineer @SPD Technology

Role Description

As a Signal Integrity/Power Integrity Engineer you will work to shape the future of AI/ML hardware acceleration by driving cutting-edge TPU (Tensor Processing Unit) technology that powers the most demanding AI/ML applications. You will be part of a team developing custom silicon solutions, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will lead chip and package design, ensuring optimal SI/PI performance and system co-design from concept to production, while collaborating within a cross-functional team of Chip Design, IP, System Design, software, and vendors.

As a qualified expert you will:

• Lead signal integrity (SI) and power integrity (PI) analysis and optimization for High-Performance Computing (HPC) leveraging advanced 2.5D/3D packaging technologies.
• Partner early in product definition to influence chip floorplanning, power distribution networks (PDN/power trees), netlists, and routability tradeoffs.
• Evaluate high-speed interface IPs and develop next-generation memory interfaces across IO PHY, SI/PI, and physical design boundaries.
• Drive post-silicon validation and qualification for NPI, balancing SI/PI performance and DFM constraints to achieve final package design closure.
• Partner closely with silicon, system, and external vendor teams while developing simulation methodologies to boost modeling accuracy and efficiency.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in SI/PI design for chip/package or system PCB.
• Experience in industry SIPI modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).
• Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes.
• Experience with partnering across chip architecture, physical design, static timing analysis (STA), package, and validation teams.
• Experience in Python, MATLAB, or C++ to establish automated flows and data processing tools.

Bonus points

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Deep knowledge of SI/PI analysis for high-speed interconnects (HBMx, D2D/chiplets, PCIe, SerDes) and timing budget methodologies.
• Direct experience with silicon interposers, silicon bridges, and 3D die stacking architectures.

Benefits

• Reveal great tech solutions: Join the team of experts who create custom, cutting-edge tech solutions for world-renowned businesses, fueling clients' growth. Unleash your potential, tackle new challenges, and be part of a team that values your skills and contributions.
• Experience an agile and flexible working environment: Work fully remote around the globe, or in a hybrid work model from our office hubs which are equipped with everything needed for comfortable work. Enjoy a flexible working schedule and create work and rest balance for yourself.
• Embrace the opportunity for personal and professional growth: Take advantage of performance review and career path. Elevate your skills with mentorship program, personal development plan, and individual learnings through the corporate library, public speaking support, and more.
• Feel cared about: Be among like-minded people and feel supported with collaboration, open communication and mutual respect. Join company-wide tech and cultural events, and contribute to meaningful CSR initiatives that resonate with your values.

Interview steps

• Interview with Recruiter
• Manager Interview
• Client Interview