[Hiring] Senior Design Verification Engineer @Capgemini

Role Description

Presently we expand our Ukraine VLSI team. You'd be able to work on projects in one team with Ukrainian engineers. Our Senior staff is open for knowledge sharing on a daily basis.

• Own verification of IP’s and SoC’s in prototype and SoC design environment;
• Establish functional and performance benchmarks;
• Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms;
• IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.

Qualifications

• Sound knowledge of SystemVerilog, and good experience in Constrained Random and Coverage Driven Verification with UVM/OVM;
• Experience in creating any UVC components or sequences is a must;
• Basic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc. Expertise in one protocol is a must for Senior and above;
• Should be comfortable in updating the existing verification environment for feature updates. (Bring-up/Architect UVM based Test bench from Scratch is a strong plus);
• EDA simulation/debugging tools agnostic;
• Good knowledge of Perl/TCL/Python scripting;
• Domain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile.

Benefits

• Competitive Salary & Benefits;
• Knowledge and support from more experienced engineers;
• Respect for your private life and your choices;
• All tools required for high performance in your field;
• Responsible approach, long term commitments, and stability;
• Health insurance from the first days, regardless of the probationary period;
• The Gift from the Company - Christmas holidays from December 25 to December 31;
• Cooperation with Superhumans center and Veteran HUB.