[Hiring] Lead ASIC DFT Engineer @Sapsol Technologies Inc

Role Description

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across:

• DFT architecture
• Scan insertion
• ATPG
• MBIST/LBIST
• JTAG
• Boundary scan
• Post-silicon validation

The ideal candidate will have strong hands-on expertise in:

• DFT fundamentals
• Fault models
• Test coverage
• Diagnosis and debug

Additionally, the candidate should have the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Qualifications

• Strong hands-on experience in ASIC DFT with end-to-end ownership.
• Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
• Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
• Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
• Experience with MBIST implementation and verification; SMS experience preferred.
• Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
• Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
• Proven post-silicon debug and silicon bring-up experience.
• Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
• Strong communication skills and the ability to work independently with minimal ramp-up.

Company Description