[Hiring] Ethernet Scale-Up RTL Lead / Principal Engineer @TYLsemi

Role Description

TYLsemi is developing purpose-built connectivity chiplet for HPC/rack-scale AI systems. We are seeking a Principal Engineer Ethernet Scale-up to lead the architecture and design of next-generation Ethernet Scale-Up Networking (ESUN) solution. This is a high-impact technical role.

• Define architecture for Ethernet-based AI scale-up interconnects and accelerator fabrics.
• Lead development of high-performance Ethernet Subsystem microarchitectures including:
  • RDMA
  • Packet processing
  • Network offload
  • Traffic management
  • Congestion control
  • Reliability mechanisms
• Drive execution from architecture through RTL, verification, physical design, silicon bring-up, and production.
• Optimize performance, latency, scalability, power, and reliability for demanding AI and HPC workloads.
• Collaborate across hardware, firmware, software, and system teams to deliver industry-leading AI networking solutions.
• Serve as a company-wide technical leader, influencing product strategy, roadmap, and architectural direction.

Qualifications

• 15+ years of ASIC/SoC architecture and design experience.
• Proven track record delivering networking, NIC, switch, DPU, accelerator interconnect, or high-speed connectivity silicon.
• Deep expertise in SystemVerilog/RTL design and high-performance datapath architecture.
• Strong knowledge of Ethernet, RDMA, traffic management, congestion control, and scalable fabric architectures.
• Experience across the full ASIC lifecycle, from architecture to production silicon.

Requirements

• Good to Have:
  • Ultra Ethernet, UALink, RoCEv2, InfiniBand
  • PCIe Gen6/Gen7, UCIe, CXL
  • AI/HPC interconnects and collective communication acceleration
  • 400G/800G/1.6T Ethernet systems
  • High-speed SerDes and advanced networking architectures

Success in This Role Looks Like

• Ethernet Scale-Up Networking architecture is defined and validated for next-gen HPC/rack-scale AI systems, with clear technical direction across accelerator fabrics.
• High-performance Ethernet subsystem microarchitecture (RDMA, packet processing, offload, traffic management, congestion control) is delivered on schedule and meets production-quality reliability bars.
• Programs move cleanly from architecture through RTL, verification, physical design, and silicon bring-up with minimal rework.
• Performance, latency, power, and reliability targets are met or exceeded for demanding AI/HPC workloads.
• Cross-functional teams (hardware, firmware, software, systems) are aligned and unblocked, with this role recognized as a trusted technical authority shaping product strategy and roadmap.