[Hiring] Design Verification Solution Architect @Capgemini

Role Description

Define and lead verification strategy for complex SoCs and subsystems, ensuring verification closure from specification through tapeout using scalable methodologies.

• Define SoC/IP verification architecture and strategy.
• Establish verification plan and coverage model.
• Guide UVM-based verification environments.
• Lead subsystem and full-chip verification.
• Drive low-power, performance, emulation, and FPGA verification.
• Conduct verification reviews with customers.
• Support methodology standardization and automation.

Qualifications

• 12+ years in verification.
• Led multiple SoC verification programs to tapeout. SoC level DV Experience is a must.
• Expert in UVM, SystemVerilog, Assertions.
• Experience in SoC boot verification using Boot Code.
• Strong coverage-driven verification expertise.
• Experience with ARM/RISC-V based compute Sub-Systems, Security Sub-system, NoC, Debug, etc.
• Knowledge of emulation based acceleration with Palladium, Zebu or Veloce.
• Familiarity with PCIe, DDR, Ethernet, UCIe or similar high-speed protocols.
• AI-assisted verification flows.

Requirements

• Formal verification.
• Security verification.
• Functional Safety verification.
• Portable Stimulus (PSS).
• Hardware/software co-verification.
• HBM/HMC memory systems.

Benefits

• We value flexibility and support our employees with remote work options and adaptable schedules to maintain a healthy work-life balance.
• Our inclusive culture brings together diverse professionals committed to growth, innovation, and excellence.
• You’ll have access to continuous learning opportunities and certifications in emerging technologies like cloud and AI.