[Hiring] Design Verification Engineer @IntelliPro Group

Role Description

As a Senior Verification Engineer on the ASIC & Networking team, you support TeraWave's first in-house silicon program, which comprises a high-throughput modem and a DSP-intensive digital beamformer with first tapeout targeted for 2027. Verification strategy, methodology, and infrastructure are being defined now, and you help define them. The work spans IP, subsystem, and full SoC verification, including:

• CPU subsystems
• Performance-critical interconnects
• Security
• High-speed peripherals
• Modem datapath and PHY layers
• DSP and beamforming compute
• Mixed-signal interfaces

You own a subset of this scope aligned to your background. The team treats constrained-random simulation, formal methods, and processor-driven SoC testing as equal first-class tools, and is building an AI-enabled verification platform that includes:

• LLM-assisted stimulus and testbench generation
• Automated regression triage and failure clustering
• Data-driven coverage closure

Because none of this is inherited, the engineers who build these capabilities will own them - and grow with the program as it scales. Background in wireless communications, modem, baseband, and DSP verification is welcome but not required. Architects and modeling engineers support your ramp, and verification judgment and system-level thinking are weighted above domain background.

Responsibilities:

• Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.
• Translate design specifications into verification strategies, measurable coverage goals, and early identification of high-risk scenarios.
• Select verification methods for each problem, including constrained-random simulation, formal analysis, and directed testing.
• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.
• Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results.
• Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels.
• Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics.
• Review testbench architecture and debug methodology, and mentor junior engineers in verification methodology.

Qualifications

• 7+ years of experience.
• BS in Engineering.
• UVM and system error log.
• CC++.

Requirements

• Taking ownership and being able to operate when the specs are not clear yet.
• Comfort in ambiguity.

Benefits

• Mentorship & Growth: A dedicated career path and mentorship from senior engineers to help you achieve your goal of becoming a full-stack developer.
• Modern Technology: The opportunity to work with a cutting-edge, in-demand technology stack.
• Supportive Culture: A collaborative and inclusive environment where learning is prioritized and contributions are valued.