[Hiring] Custom Layout Engineer @Analogue Insight

Role Description

We are seeking a highly skilled Custom Layout Engineer to play a key role in delivering high-quality analog and mixed-signal IP for our chiplet-based solutions. You will take ownership of layout execution from early planning through tape-out, working closely with analog designers to ensure performance, robustness, and manufacturability across advanced technology nodes. This role is well suited to engineers who enjoy deep, hands-on technical ownership and working closely with design teams in a fast-moving, high-impact environment.

Key Responsibilities

• Analog & AMS Layout Ownership: Lead layout activities for analog, mixed-signal, and AMS blocks and macros, ensuring high-quality, robust, and manufacturable implementations.
• Advanced Node Layout: Apply low-parasitic and high-frequency layout techniques across planar and FinFET technologies, ensuring performance and reliability at advanced nodes.
• Verification & Sign-off: Perform and support DRC, LVS, extraction, EMIR, ESD/LUP, and PERC verification, addressing issues efficiently and thoroughly.
• Collaboration with Design Teams: Work closely with analog and mixed-signal designers to understand circuit intent, constraints, and trade-offs, translating them into optimal physical implementations.
• Scripting & Automation: Develop and maintain scripts (e.g. Skill/TCL) to improve layout productivity, consistency, and quality.
• Mentorship & Technical Leadership: Mentor junior layout engineers, sharing best practices and contributing to continuous improvement of layout methodologies and flows.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field
• 5–10+ years of experience in analog IC layout
• Strong understanding of analog layout concepts, parasitics, and high-frequency design techniques
• Proven experience delivering blocks and macros to successful, high-quality tape-out
• Hands-on experience with planar technologies (e.g. 28/22 nm) at TSMC and/or GlobalFoundries
• Hands-on experience with FinFET technologies (e.g. 16/7/6 nm) at TSMC
• Exposure to multiple foundries (e.g. TSMC, Samsung, GlobalFoundries)
• Proficiency with Cadence Virtuoso, Synopsys Custom Compiler, and physical verification tools such as Calibre and ICV
• Experience with EMIR, ESD/LUP, and PERC verification flows
• Skill and/or TCL scripting experience

Requirements

• Clear, structured communication in professional English—able to explain complex results concisely
• Collaborative and feedback-oriented mindset
• Demonstrated ability to mentor and guide less experienced engineers
• Strong ownership, reliability, and follow-through
• Curious, self-motivated attitude, eager to learn and explore new tools or methods
• High level of integrity and professionalism in representing the company and handling sensitive information.

Benefits

• Remote-first flexibility – work from anywhere, with flexible hours
• Equipment & setup – we’ll provide the tools you need to succeed
• High-impact projects – design real analog IP used in customer silicon
• Supportive team culture – a dedicated manager and a team of colleagues ready to help
• Competitive, transparent compensation – adjusted for your location and engagement model
• Learning & growth – AI–DLP sessions, technical deep dives, and peer-led knowledge sharing that build both technical depth and system-level perspective

Recruitment Process

• Founder Call (30 min): mutual introduction and interest alignment
• Technical Interview (60 min): fundamentals, reasoning, and problem-solving
• Presentation (45 min): short presentation on a topic of your choice, to assess clarity, structure, and confidence in presenting your work
• HR & Culture Call (45 min): values, collaboration style, and ways of working
• Offer & Next Steps (30 min): offer walkthrough, alignment on details, and next steps, discussed in a final call with the founder.