[Hiring] Design Verification Engineer @Erbity Private Limited

Role Description

We are seeking a meticulous and highly analytical Design Verification Engineer to join our distributed engineering team. In this role, you will be responsible for ensuring the structural integrity, functionality, and performance of our hardware/system designs through rigorous testing and automated validation frameworks.

• Test Strategy & Execution: Develop, execute, and refine comprehensive test plans and procedures to verify that designs meet all functional and performance specifications.
• Defect Management: Proactively identify, document, and track design defects. Collaborate closely with designers and stakeholders to drive issues to resolution.
• Data Analysis: Analyze complex test results and datasets to uncover patterns or trends, providing actionable recommendations for design optimization.
• Automation & Tooling: Design and implement automated test scripts and scalable test frameworks to maximize verification efficiency and coverage.
• Cross-functional Collaboration: Partner with engineering teams to ensure all requirements are fully validated and that designs are implemented correctly in downstream departments.
• Documentation & Compliance: Create and maintain high-quality technical documentation, including traceability matrices, test reports, and verification plans.
• Design Influence: Participate in design reviews, offering expert feedback on requirements and ensuring "design-for-testability" (DFT) principles are met.
• Hardware Description & Verification Languages: Extensive experience with SystemVerilog and UVM (Universal Verification Methodology) is required. Proficiency in Verilog or VHDL for design understanding.
• Scripting & Automation: Strong command of Python, Perl, or Tcl for developing automated test scripts and maintaining CI/CD pipelines.
• Simulation & Debugging: Proficiency with industry-standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, or Siemens Questa). Expertise in debugging using Verdi or similar waveform viewers.
• Verification Techniques: Experience with constrained-random verification, assertion-based verification (SVA), and functional coverage (code and covergroups).
• Protocol Knowledge: Familiarity with high-speed interface protocols such as PCIe, AMBA (AXI/AHB), USB, or DDR.

Qualifications

• Extensive experience with SystemVerilog and UVM.
• Proficiency in Verilog or VHDL.
• Strong command of Python, Perl, or Tcl.
• Proficiency with industry-standard EDA tools.
• Experience with constrained-random verification and assertion-based verification.
• Familiarity with high-speed interface protocols.

Requirements

• Meticulous and highly analytical mindset.
• Ability to develop and execute comprehensive test plans.
• Strong collaboration skills with engineering teams.
• Expertise in debugging and simulation tools.