[Hiring] ASIC Synthesis and Timing Engineer @K2 Space

Role Description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply.

We are looking for an ASIC Synthesis and Timing Engineer to work on implementation of complex SoCs for next-generation satellite and space systems. You will:

• Develop the timing constraints and validate them—from RTL handoff to synthesis.
• Collaborate closely with architecture, RTL design, DFT, and physical design teams.
• Be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners.
• Develop and implement new SoC sub-systems for satellite communications and beyond.
• Contribute to developing cutting-edge SoCs that will fly in space.

Responsibilities

• Work on the RTL-to-Synthesis flow: Do synthesis at block and top level, work with physical design team to integrate the floorplan information for physical synthesis.
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end engineers to assure timing closure and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Own Lint, CDC and UPF checks and drive collaboration to close out issues.
• Develop an end-to-end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the post-layout netlist.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 2+ years of experience in ASIC design for high-performance blocks of SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with Synthesis, constraints development.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience in design convergence with offshore/outsourced PD teams or vendors.
• Able to resolve formal verification issues.
• Able to analyze and fix VCLP issues regarding UPF.
• Experience with Logic equivalence check debug, Functional ECO development and implementation with minimal database disruption, Low power checker to validate UPF.
• Familiarity with DFT integration, STA sign-off with functional ECO implementation.
• Excellent communication, leadership, and cross-functional collaboration skills.

Nice to Have

• Exposure to radiation-hardened or space-qualified ASICs.
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Benefits

• Base salary range for this role is $130,000 – $200,000 + equity in the company.
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level.
• Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.