[Hiring] ASIC Design Team Lead @Arcfield

Role Description

The successful candidate is a recognized expert who designs, researches, and develops highly advanced applications supporting Arcfield’s secure processing projects.

• Lead a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components.
• Finish developing, enhancing, and debugging the VHDL/Verilog for the chip.
• Verify the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus.
• Perform clock domain crossing (CDC) and reset domain crossing (RDC) verification.
• Perform Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design.
• Develop and port the RTL to an FPGA prototyping board.
• Perform place and route of the netlist prior to tapeout, including clock tree synthesis (CTS).
• Help the design team run static timing analysis and power analysis after the CTS and place and route.
• Package and evaluate the board for the physical chip.
• Supervise the development and maintenance of technical procedures, documentation, and manuals.
• Lead the Design team to compile and analyze operational data and direct tests to establish standards for new designs or modifications to existing equipment, systems, or processes.
• Coordinate and consult with research engineers or scientists and customer representatives to resolve design problems.

Qualifications

• Bachelor degree in Hardware or Electrical Engineering (EE) with 12-15 years of experience, or a Master's degree in Hardware or Electrical Engineering (EE) with 10-13 years of experience, or a Ph.D in Hardware or Electrical Engineering (EE) with 10+ years of experience.
• Must be able to obtain and maintain a Secret clearance.
• Minimum 3 years experience with targeting VHDL designs to Xilinx FPGAs.
• Minimum 3 years experience using Cadence Virtuoso.
• Minimum 5 years experience developing in VHDL and Verilog (or System Verilog).
• Minimum 3 years experience using ModelSim/QuestaSim.

Requirements

• Projected compensation range: Min: $130,611.87, Max: $239,061.79.
• Factors impacting final salary/hourly rate include Contract Wage Determination, relevant work experience, skills and competencies, geographic location (for remote opportunities), education and certifications, and Federal Government Contract Labor categories.

Benefits

• Health Insurance
• Life Insurance
• Paid Time Off
• Holiday Pay
• Short Term and Long-Term Disability
• Retirement and Savings
• Learning and Development opportunities
• Wellness programs
• Other optional benefit elections

EEO Statement

We are an equal opportunity employer and federal government contractor. We do not discriminate against any employee or applicant for employment as protected by law.