ASIC Design Engineer III @Arcfield
Software Development
Salary $82,437.89 - $1..
Remote Location
Job Type full-time
Posted 3d ago

[Hiring] ASIC Design Engineer III @Arcfield

3d ago - Arcfield is hiring a remote ASIC Design Engineer III. πŸ’Έ Salary: $82,437.89 - $198,097.02 πŸ“Location: Finland

Role Description

The successful candidate should be at the Career level with a complete understanding and wide application of technical principles, theories and concepts. Working under only general direction, provides technical solutions to a wide range of difficult problems.

  • Part of a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components.
  • Finish developing, enhancing, and debugging the VHDL/Verilog for the chip.
  • Verify the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus.
  • Perform clock domain crossing (CDC) & reset domain crossing (RDC) verification.
  • Implement Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design.
  • Develop and port the RTL to an FPGA prototyping board.
  • Perform place and route of the netlist prior to tapeout, including clock tree synthesis (CTS).
  • Run static timing analysis and power analysis after the CTS and place and route.
  • Package and evaluate the board for the physical chip.
  • Develop and maintain technical procedures, documentation, and manuals.
  • Compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes.

Qualifications

  • Bachelor's (or equivalent) with 5-7 years of experience, or a Master's with 3-5 years of experience, or a PhD with 0-2 years of experience.
  • Must be able to obtain and maintain a Secret clearance.
  • Minimum 3 years experience with targeting VHDL designs to Xilinx FPGAs.
  • Minimum 3 years experience using Cadence Virtuoso.
  • Minimum 5 years experience developing in VHDL and Verilog (or System Verilog).
  • Minimum 3 years experience using ModelSim/QuestaSim.

Requirements

  • Projected compensation range: Min: $82,437.89, Max: $198,097.02.
  • Factors impacting final salary/hourly rate include Contract Wage Determination, relevant work experience, skills and competencies, geographic location (for remote opportunities), education and certifications, and Federal Government Contract Labor categories.
  • Arcfield invests in its employees beyond just compensation, offering benefits such as Health Insurance, Life Insurance, Paid Time Off, Holiday Pay, Short Term and Long-Term Disability, Retirement and Savings, Learning and Development opportunities, wellness programs, and other optional benefit elections.

EEO Statement

We are an equal opportunity employer and federal government contractor. We do not discriminate against any employee or applicant for employment as protected by law.

Before You Apply
️
remote Be aware of the location restriction for this remote position: Finland
β€Ό Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
ASIC Design Engineer III @Arcfield
Software Development
Salary $82,437.89 - $1..
Remote Location
Job Type full-time
Posted 3d ago
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remote Be aware of the location restriction for this remote position: Finland
β€Ό Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
Apply for this position
Did not apply βœ“
Applied βœ“
Sent Follow-Up βœ“
Interview Scheduled βœ“
Interview Completed βœ“
Offer Accepted βœ“
Offer Declined βœ“
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