[Hiring] Sr. FPGA Developer @Fairwinds Technologies

Role Description

We are seeking an FPGA Design Engineer with strong experience developing programmable logic solutions using Xilinx Vivado, Verilog, and VHDL, targeting Xilinx Zynq UltraScale+ RFSoC, MPSoC, and Versal platforms. The ideal candidate has hands-on experience designing, implementing, and validating FPGA-based signal processing, RF data path, and high-speed data movement architectures. This includes:

• Implementing complex DSP algorithms provided by DSP engineers.
• Integrating with high-speed data converters (e.g., Analog Devices ADRV series, Texas Instruments AFE/ADC).
• Designing multi-sample per clock architectures for wideband RF applications.

This role focuses on programmable logic (PL) development, including:

• RTL design, simulation, synthesis, timing closure, and hardware validation on PCB-based platforms.
• Collaboration across hardware, DSP, RF, and embedded Linux/software domains.

This position reports to the Chief Technology & Strategy Office and involves close collaboration with customers and engineering teams to deliver innovative solutions for RF Tactical & Naval Military Solutions, as well as strategic border protection applications.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in FPGA design and development.
• Strong proficiency in Verilog and/or VHDL.
• Deep experience with RTL simulation tools such as Siemens Questa and Vivado Simulator.
• Hands-on experience using Xilinx Vivado for synthesis, implementation, timing closure, and debug.
• Hands-on experience with Xilinx Zynq UltraScale+ RFSoC a must; experience with Versal devices and other devices within the UltraScale+ family strongly preferred.
• Experience developing FPGA designs for PCB-based embedded systems.
• Experience implementing complex DSP designs provided by DSP engineers, translating algorithm specifications into efficient RTL implementations.
• Strong understanding of AXI protocols, clock domain crossing (CDC), resets, and timing constraints.
• Experience with FPGA debug tools such as ILA, VIO, and JTAG-based debugging.
• U.S. Citizenship and an active DoD Secret (or higher) security clearance (or ability to obtain).
• Experience integrating FPGA designs with high-speed data converters from Analog Devices (e.g., ADRV9009, AD9081) or Texas Instruments AFE/ADC products.
• Experience designing multi-sample per clock (parallel sample) architectures for high-throughput signal processing.
• Fundamental understanding of RF signal processing concepts including sampling theory, digital mixing, filtering, and frequency conversion.

Requirements

• Experience with Versal ACAP architecture, including heterogeneous compute resources (PL, AI Engines, hardened blocks).
• Experience implementing or integrating high-speed interfaces (JESD204B/C, Ethernet, PCIe, Aurora, or similar) in RF data converter applications.
• Strong understanding of DSP concepts and fixed-/floating-point implementation tradeoffs in FPGA designs.
• Familiarity with FPGA power optimization and performance tuning techniques.
• Scripting experience (Tcl and/or Python) for build automation, constraints generation, and CI workflows.
• Experience supporting DoD SBIR projects or similar government-funded R&D efforts.
• Experience with Xilinx RFSoC integrated RF data converters and RF Data Converter IP.
• Familiarity with Analog Devices reference designs and evaluation platforms (e.g., ADRV9009-ZU11EG).

Benefits

• Opportunity to work on cutting-edge technologies and innovative projects, including DoD SBIR initiatives.
• Collaborative and inclusive work environment.
• Competitive salary and benefits package.
• Professional development and growth opportunities.

Work Environment

This position is primarily performed in a traditional office environment. Some remote/hybrid work is also possible.

Physical Demands

While performing the duties of this job, the employee is occasionally required to stand; walk; sit; use hands to finger, handle, or feel objects, tools or controls; use fingers and hands to type or write; reach with hands and arms; talk or hear. Specific vision abilities required by the job include close vision, distance vision, color vision, peripheral vision, depth perception.

Position Type/Expected Hours of Work

This is a full-time, exempt position, working Monday through Friday; 40 hours per work week; occasional evening and weekend work may be required as job duties demand. Some flexibility in actual work hours may be offered.

Travel

Must be willing to travel 25–30% when required.

Work Authorization/Security Clearance

Must be eligible to work in the US and possess or obtain a Secret level clearance.

Other Duties

Please note this job description is not designed to cover or contain a comprehensive listing of activities, duties, or responsibilities that are required of the employee for this job. Duties, responsibilities, and activities may change at any time with or without notice.

AAP/EEO Statement

Fairwinds Technologies, LLC is an Equal Opportunity Employer – M/F/Veteran/Disability/Sexual Orientation/Gender Identity.