Principal Engineer - FPGA/ASIC Design @Rolls-Royce
Engineering
Salary unspecified
Remote Location
πŸ‡ΊπŸ‡Έ USA Only
Employment Type full-time
Posted 3d ago

[Hiring] Principal Engineer - FPGA/ASIC Design @Rolls-Royce

3d ago - Rolls-Royce is hiring a remote Principal Engineer - FPGA/ASIC Design. πŸ’Έ Salary: unspecified πŸ“Location: USA

Role Description

Rolls-Royce is looking for a Principal Engineer - FPGA/ASIC Design (Field Programmable Gate Arrays / Application Specific Integrated Circuit) Design Specialist to join our growing team. This is an exciting opportunity to work on flagship Rolls-Royce programs and play a vital role in solving some of the most complex and interesting technological challenges in the industry while being part of a global, multi-disciplinary team. In this role, you will travel up to 25%.

In this technical role, you will design, verify, integrate, and test FPGA/ASIC solutions, which will be integrated in current and future Rolls-Royce engine control system products. You will be responsible for developing FPGA/ASIC architectures, coding, running simulations, synthesis, creating test benches, and preparing documentation to be reviewed by certification authorities.

  • Participate in all phases of project, to produce detailed design documentation, verification plans and reports
  • The design and development of all custom digital devices (ASIC or FPGA), to support RR electronic engine control units
  • The verification of complex products that use FPGAs and/or ASICs to DO-254
  • Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools
  • Expertise achieving timing closure on FPGA designs and generating test benches
  • Evaluate the process flow including but not limited to high level design, synthesis, place and route, timing constraints and power utilization

Qualifications

  • Bachelor's degree in Electronics Engineering and/or Computer Engineering with 5+ years of experience, OR
  • Master's degree in Electronics Engineering and/or Computer Engineering with 3+ years of experience, OR
  • PhD in Electronics Engineering and/or Computer Engineering
  • Must be a U.S. Citizen

Requirements

  • Validate the FPGA hardware in the lab using test equipment (oscilloscopes, logic analyzers) and debug tools (e.g ILA, JTAG)
  • Experience in scripting with languages such as TCL, Python, Shell scripts
  • Able to work with Windows and Linux development environment
  • Demonstrable experience in version control, such as Git, SVN
  • Experience of Actel & Xilinx tool flows to implement complete designs
  • Development of model-based systems with digital engineering toolsets (MATLAB, Simulink and/or similar)
  • Knowledge of systems engineering, and robust design tools and techniques coupled with the latest model-centric development approaches
  • Experience with Cameo Systems Modeler (MagicDraw) or similar SysML modelling software

Benefits

  • Comprehensive and competitive Total Rewards package that includes base pay and a discretionary bonus plan
  • Opportunity to enroll in health, dental, vision, disability, life and accidental death & dismemberment insurance
  • Flexible spending account and health savings account
  • 401(k) retirement savings plan with a company match
  • Employee Assistance Program
  • Paid Time Off and certain paid holidays
  • Paid parental and family care leave
  • Tuition reimbursement
  • Long-term incentive plan
Before You Apply
️
πŸ‡ΊπŸ‡Έ Be aware of the location restriction for this remote position: USA Only
β€Ό Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
Principal Engineer - FPGA/ASIC Design @Rolls-Royce
Engineering
Salary unspecified
Remote Location
πŸ‡ΊπŸ‡Έ USA Only
Employment Type full-time
Posted 3d ago
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πŸ‡ΊπŸ‡Έ Be aware of the location restriction for this remote position: USA Only
β€Ό Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
Apply for this position
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Interview Scheduled βœ“
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Offer Accepted βœ“
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