[Hiring] PMTS, PEX Engineer @GlobalFoundries

Role Description

The Design Enablement Engineer, DRC/LVS/PEX is responsible for developing, qualifying, and deploying physical verification and parasitic extraction components for semiconductor Process Design Kits (PDKs). The role translates complex process and design requirements into accurate, robust, and efficient DRC, LVS, and PEX rule decks and verification flows, while advancing automation and AI/ML-assisted methodologies to improve PDK quality, development efficiency, and customer design success.

The Design Enablement Engineer develops and deploys critical PDK components that accurately represent semiconductor manufacturing processes within customer design and verification environments. The engineer will work at the intersection of:

• Process technology
• Design rules
• Device modeling
• EDA
• Circuit design
• Physical design

The role will have particular responsibility for:

• Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Parasitic Extraction (PEX) rule development, validation, release, and continuous improvement.
• Developing advanced automation and exploring AI/ML-based approaches for rule generation, test-case creation, coverage analysis, debugging, anomaly detection, and verification-flow optimization.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, Applied Physics, or a related technical field.
• Relevant experience in semiconductor PDK development, physical verification, EDA, IC physical design, parasitic extraction, or a related field, with minimum years aligned to the applicable GF career level.

Requirements

• Experience with DRC and/or LVS rule development, coding, debug, or qualification.
• Understanding of parasitic resistance and capacitance extraction, interconnect modeling, layout-dependent effects, and their impact on circuit performance.
• Working knowledge of CMOS process technologies, semiconductor devices, layout design rules, interconnect structures, and design-to-manufacturing interactions.
• Experience with industry-standard physical verification and/or extraction environments and rule-deck development methodologies.
• Experience with scripting or programming languages such as Python, Tcl, Perl, shell scripting, or equivalent for engineering automation, regression testing, and data analysis.
• Demonstrated ability to troubleshoot complex technical problems, perform structured root-cause analysis, and translate findings into robust engineering solutions.
• Up to 10% travel.
• Fluency in English Language: Written and verbal.

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Microelectronics, Applied Physics, Computer Science, or a related field.
• Experience developing and releasing production PDK DRC, LVS, and/or PEX rule decks for semiconductor technologies.
• Experience with physical verification environments such as Siemens Calibre, Synopsys IC Validator, Cadence Pegasus/PVS, or equivalent tools.
• Experience with PEX technology-file development, RC extraction, process-corner modeling, and silicon/model correlation.
• Experience developing automated regression environments, rule coverage metrics, test structures, or PDK qualification methodologies.
• Experience applying AI/ML, generative AI, or data-driven techniques to semiconductor design enablement.
• Understanding of interactions among process integration, design rules, OPC/lithography, device modeling, reliability, extraction, and circuit design.
• Experience collaborating directly with EDA vendors and internal or external design teams to develop and deploy differentiated design enablement capabilities.
• Strong written and verbal communication skills.
• Strong planning and organizational skills.

Expected Salary Range

$143,000.00 - $247,000.00. The exact Salary will be determined based on qualifications, experience and location.