[Hiring] Mixed Signal IC Layout Engineer @Tenstorrent

Role Description

Tenstorrent is looking for a Mixed Signal IC Layout Design Engineer role that involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. The role focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs.

This role is remote, based out of any in the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Qualifications

• An experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).
• Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout, and Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna).
• Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon and a strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts.
• Detail-oriented and organized, able to own complex blocks independently and collaborate effectively with circuit designers; typically hold a BSEE (or equivalent experience) with ~10+ years in analog/mixed-signal layout.

Requirements

• Execute full-custom analog/mixed-signal layout for key blocks (PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, high-speed I/Os) from schematics to manufacturable layouts.
• Develop optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, congestion, and integration into our D2D PHY.
• Apply best-known layout practices and optimize parasitics (R/C), coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals while closing DRC, LVS, ERC, DFM, and Antenna.
• Support post-layout extraction and simulation and, as a bonus, contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.

Benefits

• Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
• Tenstorrent offers a highly competitive compensation package and benefits.
• We are an equal opportunity employer.