[Hiring] FPGA Design Engineer @Mercor

Role Description

Evaluate the functionality of Vivado on Windows for FPGA and Digital Hardware Design.

• Develop and verify FPGA and RTL designs using Vivado.
• Capture and analyze screenshots with more than 2.5 megapixels using either a high-resolution monitor or a dual-monitor setup.
• Work independently to ensure timely completion of tasks without the provision of software licenses or hardware.
• Collaborate asynchronously with teams to improve design and verification processes.

Qualifications

• Experience with Vivado on Windows.
• Ability to capture screenshots with more than 2.5 megapixels.
• Access to a PC running Windows with Vivado installed.

Company Description

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.