[Hiring] Analog Layout Engineer @Arrow Electronics

Role Description

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

• Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design.
• Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields).

Qualifications

• Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7).
• Experience at Lower node (N3, N5) is critical for this position.
• Education: Bachelor’s degree.

Requirements

• Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection.
• Work Arrangement: Fully Onsite; must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.
• Location: Austin, USA (Remote-USA).

Company Description

eInfochips, an Arrow company (Fortune#154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals.

• Strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft, and Google.
• Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries.
• Acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients.