[Hiring] AI Silicon, Physical Design Engineer @Unconventional

Role Description

As a Member of Technical Staff, Physical Design Engineer, you will be a foundational member of our multi-disciplinary R&D team. We are looking for individuals who thrive at the intersection of architecture and silicon, turning novel AI concepts into high-performance, energy-efficient hardware. You will be responsible for the "back-end" realization of our novel computing platform, taking complex digital logic from RTL to GDSII.

Responsibilities

• Full RTL-to-GDSII Ownership: Lead the physical implementation of complex, high-performance blocks and top-level SoC integration. This includes floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and physical verification.
• PPA Optimization: Drive aggressive Power, Performance, and Area (PPA) targets. You will work closely with architects to influence the micro-architecture for better physical routability and timing closure.
• Sign-off & Verification: Own the final sign-off process, including Static Timing Analysis (STA), IR drop analysis (static and dynamic), Electromigration (EM), and Physical Verification (DRC/LVS/ERC).
• Methodology Development: Contribute to the development and automation of our physical design flow. Set best practices for synthesis, formal verification (LEC), and parasitic extraction to ensure first-pass silicon success.
• Cross-Functional Collaboration: Work at the interface of digital and analog design, facilitating the integration of custom analog mixed-signal blocks into the digital fabric.
• Partner Engagement: Work to evaluate potential partners that offer AI tools that could greatly improve chip design efficiency.

Qualifications

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 10+ years of industry experience in digital physical design, with a track record of successful tapeouts on modern process nodes (7nm, 5nm, or newer preferred).
• Technical Expertise:
  • Expertise in Static Timing Analysis (STA) and timing closure for high-frequency, complex designs.
  • Deep understanding of physical design challenges in advanced nodes (multi-patterning, finFET effects, low-voltage operation).
  • Proficiency in power integrity analysis and noise coupling mitigation.
• Design Flow Proficiency: Expert-level mastery of standard EDA tool suites (e.g., Synopsys Fusion Compiler/IC Compiler II or Cadence Innovus).
• Scripting Skills: Strong scripting skills in Tcl, Python, or Perl to automate design flows and data analysis.
• Communication: Excellent written and verbal communication skills, with experience managing deliverables from external vendors or design houses.

Requirements

• Preferred Qualifications (Nice to Have):
  • Experience with physical design for Machine Learning accelerators or large-scale systolic arrays.
  • Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements.
  • Hands-on experience with multi-voltage domains, UPF/CPF flows, and advanced power-gating techniques.
  • Familiarity with state of the art AI tools to accelerate chip design.

Benefits

• A comprehensive package including best-in-class health benefits.
• 401k matching.
• Truly unlimited PTO.
• Complimentary meals in our Mountain View office.