[Hiring] Senior Verification Design Automation Engineer @Cornelis Networks, Inc.

Role Description

We are hiring a Senior Verification Design Automation Engineer with strong design automation, AI based flow development, scripting, infrastructure, and verification environment experience to support the development and execution of scalable ASIC verification flows for world-class SoCs used in high-performance computing, high-performance data analytics, and artificial intelligence interconnect solutions.

• Develop, maintain, and improve AI based flows for verification infrastructure, automation frameworks, and execution environments used across block, subsystem, and SoC-level ASIC verification.
• Build and support scalable regression flows, dashboards, reporting utilities, and triage automation to improve verification productivity and visibility.
• Create and enhance scripts, tools, and integrations using Python, Perl, Tcl, shell scripting, Make, and related automation technologies.
• Support simulation, coverage, lint, formal, emulation, and continuous integration flows in collaboration with verification, design, architecture, and CAD teams.
• Manage compute, storage, license, queue, and job-dispatch related infrastructure issues impacting verification execution and turnaround time.
• Drive automation improvements that make verification environments more reliable, reproducible, debuggable, and efficient across geographically distributed teams.

Qualifications

• 8+ years of post-college experience in design automation, verification automation, CAD, infrastructure, or ASIC verification support.
• 8+ years of experience with scripting and automation using Python, Perl, Tcl, shell scripting, or similar languages.
• Experience supporting Linux-based engineering environments, source-control systems, build flows, regression execution, and EDA tool integration.
• Ability to debug automation failures, tool/runtime issues, infrastructure bottlenecks, and workflow inefficiencies in complex verification environments.
• B.S. Degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical discipline.

Requirements

• M.S. Degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical discipline (preferred).
• Experience supporting large-scale ASIC verification environments, regression farms, EDA tool flows, and distributed compute infrastructure (preferred).
• Knowledge of SystemVerilog/UVM verification methodologies and the ability to partner effectively with verification engineers (preferred).
• Experience with Github Actions, Git workflows, job schedulers, data analytics, and automation for regression management, coverage tracking, and productivity metrics (preferred).

Benefits

• Competitive compensation package that includes equity, cash, and incentives.
• Health and retirement benefits.
• Medical, dental, and vision coverage.
• Disability and life insurance.
• Dependent care flexible spending account.
• Accidental injury insurance and pet insurance.
• Generous paid holidays.
• 401(k) with company match.
• Open Time Off (OTO) for regular full-time exempt employees.
• Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.