[Hiring] Verification Engineer @Software Technology

Role Description

As a member of the design verification team, it is your job to break things. You will work with logic designers to test RTL modules using UVM and will have the opportunity to develop re-usable verification components and testbenches.

• Thrive in a collaborative environment (even while social distancing).
• Enjoy learning new techniques and approaches for verification and tooling.
• Work on machine learning acceleration hardware for Azure.
• Responsible for the on-time delivery of block-level layouts, with acceptable quality.
• Develop testbench components and stimulus using System Verilog UVM libraries.
• Start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets.
• Collaborate via design reviews and code reviews.

Qualifications

• Typically requires minimum of 2-10 years of experience in System Verilog, UVM.
• BE/B.Tech in Electronics and Communication (E&C) or Electrical or Telecom Engineering.
• ME/M. Tech in VLSI or Microelectronics is a plus.

Requirements

• Strong knowledge of Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
• Understanding of verification tools like Simulator, Synthesis etc.
• Hands-on experience on C/C++, System Verilog, UVM, SystemC, RTL.
• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
• Excellent written and verbal interpersonal skills.
• Self-motivated and great teammate.

Company Description