[Hiring] Staff SoC Design Engineer @quadric

Role Description

Quadric is building a revolutionary new processor-based SoC architecture. As a Staff SoC Design Engineer , you will get in on the ground floor as a key member of our chip design team, contributing across all stages of the SoC design and integration cycle. In this role, you will help define the SoC architecture, own subsystem development, integrate third-party IP, and drive PPA optimization to bring our next-generation platform to life.

What You'll Do

• SoC Subsystem Development & IP Integration
  • Own SoC-level subsystem development and seamless integration with third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.).
  • Contribute directly to the definition of the SoC architecture by deeply understanding its application requirements.
  • Package designs for customer releases and rapidly iterate based on customer feedback.
• PPA Optimization & Timing Closure
  • Own Power, Performance, and Area (PPA) optimization strategies at the SoC level.
  • Apply low-power digital design techniques to optimize hardware efficiency.
  • Contribute to timing closure across the full product lifecycle, spanning front-end, back-end, and final tapeout stages.
  • Balance single-stream latency against scaled throughput performance.

What Success Looks Like

• Independently own SoC subsystem development and drive measurable PPA improvements.
• Develop an in-depth understanding of the architecture and software interfaces, enabling you to debug complex issues across the full SW/HW stack.
• Successfully package and deliver design releases for customer evaluation and integration.

Qualifications

• BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience.
• Proficiency in SystemVerilog or Verilog.
• Strong background in computer architecture, low-power digital design techniques, and deep technical knowledge in at least one subsystem (Memory, I/O, or Compute).
• Proven experience with SoC subsystems (including 3rd-party IP) and working knowledge of VCS & Verilog/C Co-Simulation.

Preferred

• Experience in logic synthesis and performance modeling.
• Experience in FPGA design.
• Familiarity with automotive safety standards (ASIL) and hardware security standards.

Benefits

• The base salary range for this position is $170,000 to $230,000.
• Medical, dental, and vision insurance from day one - Premiums covered at 99% for Employees.
• Company-paid life Insurance.
• Voluntary supplemental life insurance.
• STD + LTD insurance.
• Commuter support including parking or Caltrain reimbursement.
• FSA + HSA.
• Equity with the business.
• Paid Parental Leave.
• 401(k) Retirement Plan.
• Flexible PTO.
• Winter holiday shutdown.
• Catered lunch each day in our office.
• Downtown Burlingame office location, close to shops, cafes, and local amenities.
• Collaborative, low-ego culture with significant ownership and impact.
• A work culture focused on innovative disruption.