[Hiring] Senior System-on-Chip Design Engineer @EdgeCortix

Role Description

We are seeking a highly skilled Senior ASIC Implementation Engineer to join our team. The successful candidate will be responsible for a range of key ASIC implementation tasks, including but not limited to:

• Synthesis
• Timing constraints
• Implementing ECOs
• STA
• Power intent implementation & validation
• Lint
• Power analysis
• CDC RDC Analysis & Validation

You will also model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures and contribute to implementation methodologies and flows. Specific responsibilities will be a function of project and team needs and may vary over time. In addition to implementation tasks, the successful candidate may also be asked to perform ASIC design tasks including:

• Some RTL development
• Physical design activities from floor plan definition to P&R
• Participate in creative problem solving as part of a cross-disciplinary design team

Qualifications

• BTech / MTech / PhD with 10+ years' experience in the semiconductor industry
• Experienced team lead or technical manager with experience in SoC Design and Verification
• Experience in wireless standards and connectivity, including signal processing
• Experience of SoCs based on ARM Core Architecture, RISC V, Power PC, etc.
• Understanding of high-speed peripherals like DDR, PCIe, ENET, UCIe
• Familiarity with other interfaces like QSPI, I2C, USB
• Memory subsystem architecture knowledge
• Knowledge of Neural Accelerators, CPUs, ARM subsystems, AXI/APB interfaces
• Strong domain knowledge of Clocking, System modes, Power management, debug, interconnect, security and other architectures
• Experience of working with Lint, CDC, RDC, Power Aware/Low power design
• Power management understanding
• Continuous learning and improvement
• Pushing the envelope
• Chiplet implementation and understanding of System In Package
• Knowledge of latest packaging/substrate technologies
• Die to Die interfaces knowledge

Requirements

• Key contributions to the SOC design and integration and all quality checks
• Ownership of the PPA, design constraints, Lint/CDC
• Work with different functions like verification, PD, DFT, etc. to achieve production quality Silicon
• Train and mentor fresh engineers for increased productivity
• Build strong collaboration with other R&D team members and leads across Architecture, SOC and Implementation
• Influence technical strategy to drive innovation (e.g., products, technology and/or patents)

Benefits

• Competitive compensation package
• Comprehensive paid time off, vacations and sick leaves
• Opportunity to join a well-funded fabless AI semiconductor startup disrupting the AI software and hardware co-design space
• Be an integral part of the company's growth and momentum