[Hiring] Senior Leader, Electrical Systems Architect @Qualcomm

Role Description

The Qualcomm Central Hardware Systems (CHS) team is seeking a Senior Leader, Electrical Systems Architect to define, develop, and productize next-generation high-speed electrical interconnect technologies for AI, hyperscale datacenter, networking, and HPC platforms. Locations include: Pacific Time Zone - Bay Area Remote; Portland Remote; Irvine Remote AND/OR Austin, TX.

The successful candidate will be a recognized technical leader with deep expertise in:

• 224G/448G PAM4 signaling
• SerDes architectures
• Signal Integrity (SI)
• Power Integrity (PI)
• Advanced packaging
• PCB design
• Connector technologies
• End-to-end electrical system analysis

This role will drive architecture and technology decisions spanning silicon, package, PCB, power delivery networks, connectors, cables, CPC/NPC flyover solutions, and rack-scale systems.

Key Responsibilities

• Define and drive end-to-end architecture for next-generation 224G and 448G PAM4 electrical interconnect systems, including SerDes, package, PCB, connector, cable, CPC, NPC, flyover, and rack-scale connectivity solutions.
• Lead system-level Signal Integrity (SI) and Power Integrity (PI) strategy, including channel budgeting, COM analysis, insertion loss, return loss, jitter, crosstalk, PDN design, and simulation-to-silicon correlation.
• Drive architecture, modeling, and optimization of high-speed link technologies spanning PHY/SerDes architectures, equalization techniques, FEC, channel operating margins, and system performance tradeoffs across bandwidth, reach, power, latency, and reliability.
• Partner across silicon, package, board, power, and system teams to develop and productize advanced electrical connectivity solutions leveraging advanced packaging, CPC/NPC flyover architectures, and next-generation PCB technologies.
• Provide technical leadership for future interconnect roadmaps, enabling scalable AI infrastructure through innovations in 224G/448G signaling, SI/PI methodologies, heterogeneous integration, and end-to-end electrical system design.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, Physics, or related discipline.
• 15+ years of experience developing high-speed communication, networking, or datacenter infrastructure products.
• Demonstrated success productizing 112G and/or 224G PAM4 electrical communication systems.

Technical Expertise

• Deep expertise in:
  • High-speed SerDes architectures
  • PAM4 communication systems
  • Signal Integrity (SI)
  • Power Integrity (PI)
  • Package, PCB, connector, and cable design
  • Power delivery network architecture
  • Advanced packaging technologies
  • Channel modeling and compliance methodologies
  • End-to-end electrical system architecture
  • AI networking, scale-up, and scale-out infrastructures
• Hands-on experience with:
  • ADS, HFSS, CST, HSPICE, MATLAB, Python, Cadence Sigrity, PowerSI, Clarity, SystemVerilog, Verilog-A, COM analysis tools, IBIS-AMI modeling

Preferred Qualifications

• Experience developing and productizing 224G+ and 448G electrical interconnect solutions.
• Experience with CPC, NPC, copper flyover architectures, AECs, advanced package substrates, and next-generation PCB technologies.
• Familiarity with Ethernet, PCIe, UALink, NVLink, OIF CEI, IEEE 802.3, and AI networking fabrics.
• Experience with chiplets, UCIe, heterogeneous integration, EIC/PIC interfaces, and advanced packaging technologies.
• Track record influencing technology roadmaps, industry standards, and large cross-functional architecture decisions.
• Proven technical leadership and mentorship of senior engineering teams.

Minimum Qualifications

• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 10+ years of System/Package Design/Technology Engineering or related work experience.
• OR Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 9+ years of System/Package Design/Technology Engineering or related work experience.
• OR PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 8+ years of System/Package Design/Technology Engineering or related work experience.

Benefits

• Pay range: $256,600.00 - $385,000.00
• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play.