[Hiring] Senior CAD Semiconductor Engineer @Capgemini

Role Description

Assumptions: This Job Description document is mainly for a Senior CAD Engineer / Technical Lead. Leadership expectations can be adjusted for more junior roles with increased hands-on focus.

Mission:

• Define, deploy, and maintain EDA tool flows and CAD infrastructure supporting semiconductor design and verification activities across full SoC lifecycle.
• Drive the evaluation, benchmarking, and integration of EDA tools (Cadence, Synopsys, Siemens EDA, Arteris) and associated flows to maximize productivity, reliability, and scalability.
• Own the engineering infrastructure environment (compute, storage, licensing, CI/CD, automation) required for advanced chip design workloads.
• Collaborate with design, verification, and physical implementation teams to ensure efficient, robust, and scalable tool usage.
• Explore and integrate AI/ML-based tooling and workflows to improve engineering productivity (automation, debugging, optimization, knowledge extraction).
• Ensure optimal trade-offs between performance, cost, scalability, and usability of the CAD environment.
• Act as a key technical interface between internal engineering teams, management, and EDA vendors.
• Provide regular reporting on tool performance, usage, and roadmap alignment.

Main responsibilities:

• Define, deploy, and maintain EDA flows for digital, mixed-signal, and verification activities (simulation, synthesis, P&R, DFT, signoff).
• Evaluate, benchmark, and qualify new EDA tools, releases, and methodologies before production deployment.
• Design and operate EDA infrastructure environments, including:
  • Compute farms (Linux-based clusters for simulation and regression)
  • Storage systems (NFS, distributed storage, backup/DR)
  • License servers (FlexLM/Flexera).
• Develop and maintain automation frameworks for:
  • Tool installation and configuration
  • Regression and CI/CD pipelines
  • Resource provisioning and monitoring.
• Implement and manage CI/CD pipelines (e.g., Jenkins, GitLab CI) for design and verification workflows.
• Collaborate with engineering teams to:
  • Optimize tool usage and flows
  • Debug tool-related issues
  • Improve turnaround time and efficiency.
• Maintain strong interaction with EDA vendors (Cadence, Synopsys, Siemens):
  • Tool support, issue resolution, roadmap alignment
  • Licensing strategy and capacity planning.
• Define and enforce best practices and standards for CAD usage and tool flows.
• Integrate AI-driven capabilities into engineering workflows, including:
  • LLM-assisted scripting and automation
  • AI-based log analysis, debug assistance, and workflow optimization
  • Hybrid cloud/on-prem AI infrastructure for sensitive data
  • Support security, compliance, and reliability requirements (e.g., ISO 27001 environments).

Qualifications

• Strong experience with full EDA flows: Simulation, synthesis, place & route, verification, DFT flows.
• Tools from Cadence, Synopsys, Siemens EDA (Mentor Graphics).
• Tool validation, qualification, and deployment.
• Strong experience with EDA licensing systems (FlexLM/Flexera).
• Tool versioning, release management, and regression validation.
• Good understanding of RTL design, verification flows, and physical design constraints.
• Interaction between tools and silicon quality/productivity.
• Knowledge in ISO26262, DO-254 is a plus.

Requirements

• Master’s degree (or equivalent) in Microelectronics, Electrical Engineering, or related field.
• 8–15+ years in CAD / EDA / semiconductor infrastructure.
• Proven experience in EDA tool deployment and flow ownership.
• Strong exposure to semiconductor design environments.
• Strong ownership and autonomy in managing complex engineering environments.
• Ability to bridge design teams and infrastructure/tooling domains.
• Excellent problem-solving and analytical skills.
• Clear communication with both technical and non-technical stakeholders.
• Proactive mindset with focus on automation and continuous improvement.
• Ability to challenge existing approaches and drive pragmatic, scalable solutions.

Benefits

• Health insurance from the first days, regardless of the probationary period.
• Christmas holidays from 25 December to 31 December.
• Cooperation with Superhumans center and Veteran HUB.
• Support for psychological counseling provided by the Veteran Hub.
• Internal policy making the company friendly to military and veterans.