[Hiring] Principal FPGA Networking Engineer @TRIDENT SYSTEMS LLC

Role Description

The Principal FPGA Networking Engineer plays a critical role in the design and development of advanced FPGA-based networking solutions supporting space-based electronic systems. This position is responsible for architecting, implementing, and verifying complex, high-speed programmable logic designs for on-board networking, data transport, and packet processing functions using the latest AMD (Xilinx) technologies.

• Work within a multi-discipline team of engineers designing on-board networking, data transport, RF, processing, and data storage solutions for space applications utilizing AMD (Xilinx) technologies (e.g., Zynq UltraScale+ MPSoC, Zynq UltraScale+ RFSoC, Versal ACAP).
• Architect FPGA-based networking pipelines including Ethernet MAC/PHY integration, packet parsing/classification, switching/forwarding, buffering, and QoS mechanisms for high-reliability space systems.
• Design and implement packet switching fabrics, router/switch datapaths, control logic, and buffering/queuing schemes to support high-throughput, low-latency transport across multiple interfaces and protocols.
• Create and maintain complete FPGA designs using VHDL and Vivado IP Integrator with emphasis on efficient networking data-path architecture, deterministic latency, and reliable timing closure.
• Code, simulate, and verify RTL modules such as Ethernet MAC/PHY interfaces (IEEE 802.3), packet processing blocks, switching/routing/queuing logic, and control interfaces to peripherals and system controllers.
• Design and implement solutions that use embedded ARM processors, DDR4 memory, and high-speed serial interfaces (e.g., Aurora, PCIe, multi-rate Ethernet) to ensure robust data movement within and between FPGA-based subsystems.
• Implement and optimize hardware support for networking protocols and stacks (e.g., IP, TCP/UDP, VLAN, QoS), including offload engines and checksum/segmentation logic.
• Develop and maintain simulation testbenches to ensure high code coverage and verify functional correctness, robustness, and performance of networking firmware modules.
• Define and maintain timing constraints and perform timing closure for multi-clock, multi-interface networking designs.
• Develop and maintain IP core-level and top-level design documentation, interface control documents, and performance characterization reports (e.g., throughput, latency, packet loss, resource utilization).
• Participate in code and design reviews, and contribute to FPGA design methodologies and best practices for high-performance networking and packet processing.
• Collaborate closely with hardware and software engineers to integrate FPGA networking designs with system hardware, drivers, and higher-level networking stacks.
• Support board bring-up and system verification in an electronic lab environment, including link bring-up, traffic generation, protocol compliance testing, network performance evaluation, and system-level debug using FPGA ILA-based tools (Vivado HW Debugger, Chipscope, SmartDebug).
• Mentor junior engineers in FPGA networking architecture, protocol implementation, buffering/queuing strategies, and verification best practices.

Qualifications

• Bachelor’s degree in Computer Engineering, Electrical Engineering or related technical degree.
• 9+ years of related experience with a bachelor’s degree OR a 7+ years of experience with a master’s degree.
• Hands-on experience with FPGA-based networking design, including Ethernet (IEEE 802.3), high-speed serial links, and packet-switched architectures.
• Experience implementing or integrating networking protocols and functions in hardware (e.g., IP, TCP/UDP, VLAN, QoS, router/switch datapaths, routing look-up tables).
• Experience with firmware/RTL design, simulation, and verification for complex, high-throughput FPGA systems.
• Experience with RTL logic design and coding using VHDL and/or Verilog.
• Thorough understanding of FPGA design methodology including physical synthesis, static timing analysis, place/route, verification, power analysis, and timing closure techniques.
• Experience writing simulation testbenches to identify bugs and verify designs.

Preferred Qualifications

• Deep understanding of data networking architectures, routers, switches, and network management concepts.
• Experience with high-speed Ethernet interfaces, including 100G Ethernet, in FPGA-based designs.
• Experience with multi-level security networking concepts and architectures.
• Experience with network security protocols and mechanisms such as IPsec and MACsec, particularly in embedded or FPGA-based implementations.
• Experience designing and verifying buffering and queuing schemes in hardware (e.g., FIFOs, circular buffers, priority queues) to support high-throughput, low-latency packet transport.
• Experience with networking test and qualification, including link-level and end-to-end networking performance and protocol compliance testing.
• Experience designing with AMD (Xilinx) SoC/FPGA devices using the Vivado Design Suite.
• Experience using Vivado IP Integrator.
• Experience designing with Microsemi (Microchip) FPGAs using Libero.
• Experience using Modelsim/Questasim and/or Aldec simulation tools.
• Experience using simulation verification libraries such as UVVM, UVM, OVM, etc.
• Experience with board bring-up and verification in an electronic lab environment, including use of standard lab equipment (logic analyzers, oscilloscopes, signal/spectrum analyzers, Ethernet traffic generators) and FPGA ILA-based debugging tools (e.g., Vivado HW Debugger, Chipscope, SmartDebug).
• Experience using revision control systems, such as Git.
• Highly productive, self-motivated person able to contribute as an individual and work within a distributed team.
• Experience with Linux.
• Experience with C/C++.

Benefits

• Health benefits
• Medical
• Dental
• Vision
• Basic life with AD&D
• Short term disability
• Long term disability
• Ancillary (Voluntary life with AD&D, accident, critical illness, hospital, and pet)
• Spending accounts (HSA, FSA, and DCFSA)
• Paid time off
• Holidays
• 401(k) (including company match)
• Tuition reimbursement
• Leaves (Parental, maternity, and military)
• Annual discretionary bonus (for eligible roles)