[Hiring] Principal ASIC DFT Design Engineer @BLUE ORIGIN

Role Description

As a Principal ASIC DFT Designer on the ASIC Engineering SOC Team, you will own design for test architecture for the TeraWave System on Chip (SOC) program. You will define the test strategy for large multi-block SOC designs, implement scan, compression, and built in self test infrastructure, and deliver the test vectors that qualify silicon on automated test equipment. This is a senior individual contributor role with technical leadership scope and no direct reports. Your work spans specification through silicon bring up, including ATE pattern debug and support for defect and yield analysis, and it directly determines test quality and manufacturability for the program.

• Define DFT architecture and test strategy for large multi-block SOC designs
• Author DFT specifications covering scan, compression, boundary scan, and test access mechanisms
• Implement scan chain insertion, test clock control, and on chip compression logic
• Design memory and logic built in self test infrastructure for embedded memories and logic
• Generate and validate DFT vectors for silicon bring up and production test programs
• Debug ATE pattern failures and drive resolution with design and product engineering teams
• Support defect analysis and yield improvement using test coverage and silicon failure data
• Review test coverage and DFT timing metrics with physical design and verification teams

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• Minimum 10 years of experience in design for test for complex digital SOCs
• Experience defining DFT architecture and specifications for large multi-block SOC designs
• Experience with DC and AC scan design and memory built in self test implementation
• Experience generating ATPG patterns for automated test equipment and debugging ATE patterns

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, or related technical field
• Experience with logic built in self test implementation and signature based test methodologies
• Experience with defect analysis and yield improvement for advanced process node silicon
• Experience with hierarchical DFT and IEEE 1500 or IEEE 1687 test access standards
• Experience with commercial DFT tool flows such as Tessent, DFTMAX, or Modus
• Experience with test time and test cost reduction through pattern and compression optimization
• Strong written and verbal communication skills for presenting test strategy to technical stakeholders

Benefits

• Medical, dental, vision, basic and supplemental life insurance
• Paid parental leave
• Short and long-term disability
• 401(k) with a company match of up to 5%
• Education Support Program
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion