[Hiring] Principal Analog Mixed-Signal Design Engineer @TYLsemi

Role Description

As an Analog Design Engineer at Tylsemi, you will design and deliver high-performance analog and mixed-signal circuits that enable robust, manufacturable silicon. This role spans a wide experience range (5–30 years) and is ideal for engineers who combine strong fundamentals with practical execution—translating system requirements into silicon-ready designs, validating performance across corners, and partnering closely with layout, verification, test, and product teams to drive first-time-right outcomes.

• Design of Voltage Regulators including:
  • High-efficiency power stages
  • Error amplifiers
  • Current sensing
  • Adaptive load-line circuits
  • Fast transient compensation
  • Protection and telemetry
• Modeling of mixed-signal subsystems including:
  • Regulator control loops
  • Power delivery network
  • DVFS subsystems
• Lead the collaboration with SIPI/PI, packaging teams to co-optimize VR and power delivery.

Qualifications

• 12+ years of hands-on analog/mixed-signal IC design experience with a strong focus on high-current, high-efficiency power management (PMIC / IVR / DC-DC converters).
• Deep expertise in different voltage regulator topologies including control loops delivering large current at high switching frequencies.
• Hands-on experience in magnetics integration for high-density IVR including inductor modeling, coupling effects, EMI/thermal co-optimization, and 3DIC package integration.
• Proficiency with industry-standard design and modelling tools including Cadence Virtuoso, Spectre, Clarity/EMX, MATLAB/Simulink.
• Experience in 2.5D, packaging flows and co-design with SIPI/PDN teams.
• Team player with excellent communication skills.
• BS / MS / PhD in Electrical Engineering (Analog & Mixed-Signal focus).

Requirements

• Experience with state-of-the-art AI/HPC power delivery.
• Familiarity with advanced packaging flow and thermal/PI co-optimization.

Success in This Role Looks Like

• Analog blocks meet spec with margin across PVT, mismatch, and post-layout effects.
• Design reviews are crisp: requirements, tradeoffs, and risks are clearly articulated and managed.
• Silicon bring-up converges quickly through strong correlation, structured debug, and decisive fixes.
• Cross-functional partners (layout, verification, test, validation) can execute efficiently with clear interfaces and documentation.
• Reusable design collateral and improved methodology reduce cycle time and increase first-pass success.