[Hiring] FPGA Verification Engineer - UVM Architect @Quest Defense Systems & Solutions
FPGA Verification Engineer - UVM Architect @Quest Defense Systems & Solutions
Engineering
Salary $150,000 - $180..
Remote Location
๐Ÿ‡บ๐Ÿ‡ธ USA Only
Employment Type full-time
Posted YDay

[Hiring] FPGA Verification Engineer - UVM Architect @Quest Defense Systems & Solutions

YDay - Quest Defense Systems & Solutions is hiring a remote FPGA Verification Engineer - UVM Architect. ๐Ÿ’ธ Salary: $150,000 - $180,000 ๐Ÿ“Location: USA

Role Description

Build the verification systems behind mission-critical FPGA designs as a Senior FPGA Verification Engineer (UVM / SystemVerilog / DO-254). This is a hands-on technical leadership role where youโ€™ll own how verification is doneโ€”from testbench architecture to coverage closureโ€”while helping teams deliver reliable FPGA designs used in real-world aerospace applications.

  • Lead development of SystemVerilog / UVM verification environments for FPGA designs
  • Build and improve testbenches, agents, scoreboards, monitors, and sequences
  • Define verification strategy, test plans, and coverage goals
  • Drive functional, code, and assertion coverage closure
  • Support both simulation and emulation workflows (Veloce or similar)
  • Review and improve existing verification environments and processes
  • Guide engineers on UVM best practices and debug complex issues
  • Support DO-254 verification activities (requirements traceability, test evidence, audits)
  • Work closely with design, systems, and program teams

Qualifications

  • 8โ€“12+ years of experience in FPGA or ASIC verification
  • Strong hands-on experience with SystemVerilog and UVM
  • Experience building UVM testbenches and reusable verification environments
  • Background in simulation, debugging, and coverage-driven verification
  • Experience with tools like QuestaSim, VCS, or similar
  • Understanding of hardware interfaces and RTL design
  • Ability to lead technical efforts and guide other engineers
  • Experience building UVM verification environments (SystemVerilog), including agents, drivers, monitors, and scoreboards
  • Ability to create self-checking simulations using predictors and coverage-based testing
  • Basic understanding of register modeling (UVM RAL) and how to test and validate register behavior in simulation
  • Experience with DO-254 or other safety-critical standards

Requirements

  • Experience with emulation tools (Siemens Veloce, Palladium, etc.)
  • Knowledge of high-speed interfaces or communication protocols
  • Experience with requirements tools (DOORS) or traceability
  • Exposure to aerospace, defense, or regulated industries
  • Experience with Python or automation scripting

Benefits

  • Competitive pay
  • Comprehensive medical/dental/life and disability coverage
  • 401(k) with employer match
  • Professional development support
  • Flexible, friendly workplace
Before You Apply
๏ธ
๐Ÿ‡บ๐Ÿ‡ธ Be aware of the location restriction for this remote position: USA Only
โ€ผ Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
FPGA Verification Engineer - UVM Architect @Quest Defense Systems & Solutions
Engineering
Salary $150,000 - $180..
Remote Location
๐Ÿ‡บ๐Ÿ‡ธ USA Only
Employment Type full-time
Posted YDay
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๐Ÿ‡บ๐Ÿ‡ธ Be aware of the location restriction for this remote position: USA Only
โ€ผ Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
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