[Hiring] FPGA Emulation Engineer @Quest Defense Systems & Solutions

Role Description

Embark on a journey with QDSS at the forefront of technological innovation as we seek talented Engineers to shape the future of cutting-edge projects and contribute to a culture of excellence and creativity.

Quest Defense Systems & Solutions (QDSS) is seeking a Senior FPGA Emulation Engineer to build and scale hardware-accelerated verification environments for complex, safety-critical FPGA systems. This role is focused on emulation and system-level validation, not just simulation.

You’ll be working with platforms like Siemens Veloce (or similar) to:

• Accelerate verification
• Debug full-chip behavior
• Enable validation of designs that can’t realistically be verified in simulation alone

If you enjoy working close to the hardware, solving performance bottlenecks, and making large-scale FPGA systems actually testable and debuggable, this is where you want to be.

Qualifications

• 5+ years of experience in FPGA/ASIC verification or validation
• Hands-on experience with hardware emulation platforms (Siemens Veloce, Cadence Palladium, Synopsys ZeBu, etc.)
• Experience bringing up designs in emulation environments and debugging system-level issues
• Strong understanding of RTL design and verification workflows
• Experience bridging simulation ↔ emulation environments
• Ability to analyze performance bottlenecks and optimize emulation runs
• Familiarity with SystemVerilog and UVM (integration level, not pure architect focus)
• Experience debugging interfaces, data paths, and timing-related issues
• Ability to work across teams and drive technical solutions

Requirements

• Build and maintain FPGA emulation environments using Siemens Veloce or similar platforms
• Port and optimize RTL and test environments from simulation into emulation
• Debug complex system-level issues that only appear at scale or in hardware-accelerated environments
• Improve emulation performance, compile times, and runtime efficiency
• Integrate UVM-based environments into emulation workflows
• Support validation of high-speed interfaces and system-level data flows
• Collaborate with RTL, verification, and systems teams to resolve design and integration issues
• Enable full-chip and subsystem validation that cannot be achieved in simulation alone
• Support DO-254 verification activities, including traceability and test evidence where needed
• Help define best practices for emulation workflows across programs

Nice to Have

• Experience with DO-254 or other safety-critical standards
• Exposure to high-speed interfaces or communication protocols
• Experience with scripting/automation (Python, TCL, etc.)
• Experience supporting board bring-up or hardware validation
• Familiarity with coverage strategies across simulation and emulation
• Exposure to aerospace or defense programs

Benefits

• Competitive pay
• Comprehensive medical/dental/life and disability coverage
• 401(k) with employer match
• Professional development support
• Flexible, friendly workplace