[Hiring] FPGA Developer @AscendArc

Role Description

We are seeking an experienced FPGA Developer to play a critical role in developing and advancing the communications technology behind our next-generation spacecraft. This is an opportunity to take ownership of FPGA development, working across digital signal processing, software-defined radio (SDR), and spacecraft integration.

• Work with existing modulation, demodulation, and packet-switching IP cores.
• Develop custom DSP functionality and interfaces for spacecraft command, control, and communication.
• Influence technical direction and solve complex engineering challenges.
• Enjoy a highly collaborative, hands-on role with technical ownership.

Responsibilities

• Architect, write, and verify synthesizable RTL (SystemVerilog or VHDL) targeting modern FPGAs.
• Integrate and configure existing modulation and demodulation, and packet-switching/routing IP cores.
• Implement DSP blocks in fabric: FIR/CIC/polyphase filters, NCOs and mixers, decimation/interpolation chains, channelizers, and demodulation/synchronization logic.
• Develop simulation testbenches (UVM, cocotb, or similar) and drive functional and code coverage.
• Take designs through synthesis, place-and-route, and timing closure; analyze utilization, congestion, and Fmax issues.
• Integrate with ADC/DAC front-ends and other mixed-signal interfaces.
• Collaborate with systems, firmware, and hardware engineers on interface definitions and HW/SW partitioning.
• Produce design documentation, interface control documents, and verification reports.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 8+ years of professional FPGA development in SystemVerilog and/or VHDL.
• Demonstrated experience integrating third-party or vendor IP cores into larger FPGA designs.
• Working understanding of packet-based routing and switching concepts.
• Strong DSP fundamentals and hands-on experience implementing signal processing in fixed-point HDL.
• Practical experience with high-speed serial transceivers.
• Proficiency with the full Vivado toolchain.
• Strong verification skills, including self-checking testbenches and coverage-driven methodology.
• Comfort with Git-based workflows and code review.

Preferred Qualifications

• RF and analog front-end experience.
• Experience with high-speed converter interfaces such as JESD204B/C.
• Experience with space, defense, or other high-reliability environments.
• Familiarity with AXI/AXI-Stream interconnect and DMA architectures.
• Background in clock-domain crossing methodology and formal verification of CDC.
• Experience supporting hardware bring-up with lab instrumentation.

Location

Open to fully remote within the United States or hybrid in Portland, OR.