[Hiring] Design Verification Engineering Intern @Intel Corporation
Design Verification Engineering Intern @Intel Corporation
Engineering
Salary unspecified
Remote Location
Employment Type internship
Posted YDay

[Hiring] Design Verification Engineering Intern @Intel Corporation

YDay - Intel Corporation is hiring a remote Design Verification Engineering Intern. πŸ’Έ Salary: unspecified πŸ“Location: Canada

Role Description

ASIC Design & Verification Engineering Opportunity

Ready to tackle the cutting-edge challenges of modern semiconductor design? Join our dynamic verification team where you'll work on next-generation System-on-Chip (SoC) technologies that power everything from smartphones to data centers. This role offers hands-on experience with industry-leading EDA tools and methodologies while contributing to high-impact projects that shape the future of silicon innovation.

Modern SoCs have grown exponentially more complex, integrating ever more functionality onto a single silicon die and combining multiple silicon dies into sophisticated packages. ASIC design and verification methodologies must continue to advance and keep pace with this growing complexity to ensure high-quality, functional SoC designs.

As ASICs become increasingly complex to enhance functionality, performance, and power efficiency, verification processes must adapt to meet rigorous industry standards. Our team utilizes various advanced verification techniques to simulate and validate designs against ASIC specifications. You'll gain valuable experience with industry-standard EDA tools while developing skills to assess and ensure design quality.

  • Strong debugging and problem-solving skills
  • Excellent written and verbal communication skills
  • Project-based teamwork experience

Qualifications

  • Enthusiastic students with strong problem-solving abilities
  • Excellent communication skills
  • Genuine desire to learn
  • Solid foundation in digital design verification (System Verilog, VHDL) and object-oriented programming
  • Students looking for a challenging and rewarding work experience are strongly encouraged to apply

Requirements

  • Active student pursuing a Bachelor degree in Electrical, Computer Engineering or related field
  • Experience or coursework in the following:
    • Digital Logic Design and Verification
    • HVL
    • Languages: Verilog/VHDL, System Verilog
    • Programming Languages: C, C++
    • Scripting: Perl/Python, TCL
    • EDA Simulation Tools

Company Description

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars:

  • Product Enablement (IP, tools, and methodologies)
  • Custom ASIC (leveraging existing IP for custom silicon)
  • Foundry Enablement (supporting top customers and validating technologies)

The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Before You Apply
️
remote Be aware of the location restriction for this remote position: Canada
β€Ό Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
Design Verification Engineering Intern @Intel Corporation
Engineering
Salary unspecified
Remote Location
Employment Type internship
Posted YDay
Apply for this position
Did not apply βœ“
Applied βœ“
Sent Follow-Up βœ“
Interview Scheduled βœ“
Interview Completed βœ“
Offer Accepted βœ“
Offer Declined βœ“
Unlock 150,000+ Remote Jobs
️
remote Be aware of the location restriction for this remote position: Canada
β€Ό Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
Apply for this position
Did not apply βœ“
Applied βœ“
Sent Follow-Up βœ“
Interview Scheduled βœ“
Interview Completed βœ“
Offer Accepted βœ“
Offer Declined βœ“
Unlock 150,000+ Remote Jobs
Γ—

Apply to the best remote jobs
before everyone else

Access 150,000+ vetted remote jobs and get daily alerts.

4.9 β˜…β˜…β˜…β˜…β˜… from 500+ reviews
Unlock All Jobs Now

Maybe later