Advanced ASIC FPGA Verification Engineer @General Dynamics Mission Systems
Engineering
Salary usd $122,785.00..
Remote Location
πŸ‡ΊπŸ‡Έ USA Only
Employment Type full-time
Posted 2d ago

[Hiring] Advanced ASIC FPGA Verification Engineer @General Dynamics Mission Systems

2d ago - General Dynamics Mission Systems is hiring a remote Advanced ASIC FPGA Verification Engineer. πŸ’Έ Salary: usd $122,785.00 - usd $136,215.00 /yr. πŸ“Location: USA

Role Description

  • Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments.
  • Determines architecture, system simulation and detailed design approach.
  • Defines module interfaces and all aspects of device design and simulation.
  • Creates test and simulation plans that establish functional criteria.
  • Verifies test results and analyzes performance.
  • May also review vendor capabilities and simulation tools.
  • Participates in the improvement of the ASIC/FPGA organizational processes.
  • Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle.
  • May provide leadership and/or direction to lower level employees.
  • Independently determines approach to solutions.
  • Contributes to the completion of major programs and projects.
  • Plans and executes project tasks for activities described above.

Qualifications

  • Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field.
  • 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience.
  • Clear understanding of embedded micro-processing systems, FPGA Design and Verification using VHDL, and digital circuit analysis and design.
  • Collaborative, creative thinker with high proficiency in technical problem solving.
  • Team player with effective communication and presentation skills.
  • Experience designing high speed interfaces and complex memory designs.
  • Commitment to ongoing professional development for yourself and others.
  • Identifies opportunities to apply AI for continuous improvement and innovation.

Requirements

  • In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment.
  • In-depth knowledge of System Verilog, object oriented programming and the Universal Verification Methodology (UVM).
  • Understands UVM Testbench Architectures.
  • Comfortable using and developing UVM agents, bus functional models.
  • Understands different types of coverage, usage of cover classes, cover points, etc.
  • Experience with predictive testbench components, functional coverage and assertions.
  • Experience with constrained random testing.
  • Experience with the Register Abstraction Layer.
  • Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies.
  • Experience with scripting languages such as Linux shell scripts, TCL, Python.
  • Familiarity with using Formal Verification tools, code coverage, writing waivers, etc.
  • Familiarity with Questa Verification IP (QVIP).
  • Developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs.
  • AXI protocols, PCIe, Space Wire, and Ethernet interfaces.
  • DSP functions and common signal processing components.
  • Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration.
  • Continuous Integration features of GITLab.

Benefits

  • An exciting career path with opportunities for continuous learning and development.
  • Research oriented work, alongside award winning teams developing practical solutions for our nation’s security.
  • Flexible schedules with every other Friday off work, if desired (9/80 schedule).
  • Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more.

Company Description

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Before You Apply
️
πŸ‡ΊπŸ‡Έ Be aware of the location restriction for this remote position: USA Only
β€Ό Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
Advanced ASIC FPGA Verification Engineer @General Dynamics Mission Systems
Engineering
Salary usd $122,785.00..
Remote Location
πŸ‡ΊπŸ‡Έ USA Only
Employment Type full-time
Posted 2d ago
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πŸ‡ΊπŸ‡Έ Be aware of the location restriction for this remote position: USA Only
β€Ό Beware of scams! When applying for jobs, you should NEVER have to pay anything. Learn more.
Apply for this position
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Sent Follow-Up βœ“
Interview Scheduled βœ“
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