[Hiring] Advanced ASIC FPGA Verification Engineer @General Dynamics Mission Systems, Inc

Role Description

We encourage you to apply if you have any of these preferred skills or experiences:

• In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
• In-depth knowledge of System Verilog, object-oriented programming, and the Universal Verification Methodology (UVM)
• Understands UVM Testbench Architectures
• Comfortable using and developing UVM agents, bus functional models
• Understands different types of coverage, usage of cover classes, cover points, etc.
• Experience with predictive testbench components, functional coverage, and assertions
• Experience with constrained random testing
• Experience with the Register Abstraction Layer
• Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies
• Experience with scripting languages such as Linux shell scripts, TCL, Python
• Familiarity with using Formal Verification tools, code coverage, writing waivers, etc.
• Familiarity with the following are also helpful:
  • Questa Verification IP (QVIP)
  • Developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs
  • AXI protocols, PCIe, Space Wire, and Ethernet interfaces
  • DSP functions and common signal processing components
  • Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration
  • Continuous Integration features of GITLab

Duties and Tasks:

• Responsible for definition, design, verification, and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
• Determines architecture, system simulation, and detailed design approach
• Defines module interfaces and all aspects of device design and simulation
• Creates test and simulation plans that establish functional criteria
• Verifies test results and analyzes performance
• May also review vendor capabilities and simulation tools
• Participates in the improvement of the ASIC/FPGA organizational processes
• Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
• May provide leadership and/or direction to lower-level employees
• Independently determines approach to solutions
• Contributes to the completion of major programs and projects
• Plans and executes project tasks for activities described above

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field
• 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience

Requirements

• Must be able to obtain a U.S. Department of Defense TS/SCI security clearance
• U.S. citizenship is required

Benefits

• Flexible schedules with every other Friday off work, if desired (9/80 schedule)
• Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more

Company Description

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products, and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas.