[Hiring] RTL Design Engineer - AI Tools @Mercor

Role Description

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.

Position: RTL Design Engineers

Type: Contract

Compensation: $100–$175/hour

Location: Remote

Duration: 3+ months

Commitment: 40 hours/week

Role Responsibilities

• Evaluate and enhance AI model training for digital chip design and verification.
• Design and implement RTL components using Verilog/SystemVerilog.
• Develop and maintain ASIC design flows including lint, synthesis, and timing analysis.
• Collaborate with architecture, verification, and implementation teams to ensure seamless integration.
• Utilize EDA tools for simulation, waveform debug, and coverage analysis.
• Work independently and asynchronously to meet project deadlines and improve AI model performance.

Qualifications

• 3–10 years of experience in digital RTL design or design verification.
• Strong proficiency in Verilog/SystemVerilog and UVM.
• Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
• Experience with ASIC design flows and EDA tools.
• Familiarity with leveraging LLM-based tools for chip design and verification workflows.

Requirements

• Knowledge of AMBA protocols (AXI, AHB, APB).
• Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
• Exposure to formal verification or SV/UVM-based design verification.

Company Description