[Hiring] AI Silicon, DFT Engineer @Unconventional, Inc.

Role Description

As a Member of Technical Staff, DFT Engineer, you will be a foundational member of our multi-disciplinary R&D team. We are looking for individuals who thrive at the intersection of architecture and silicon, turning novel AI concepts into high-performance, energy-efficient hardware. You will be responsible for the testability realization of our novel computing platform, ensuring that our complex digital logic and custom mixed-signal blocks can be reliably tested.

Responsibilities

• DFT Architecture & Implementation: Lead the implementation of comprehensive test architectures using industry-standard CAD tools. This includes the insertion, configuration, and verification of scan compression, Memory Built-In Self-Test (MBIST), and JTAG/boundary scan logic.
• Hierarchical DFT Implementation: Drive bottom-up hierarchical DFT methodologies for large-scale SoC designs, managing core-level test wrapping, pattern retargeting, and top-level test integration to optimize runtime and capacity limits.
• Foundry Interface & Defect Analysis: Own the overarching DFT strategy, working closely with foundry interfaces to analyze defect densities and drive yield improvements for test chips.
• Multi-Stacked Die DFT: Drive cutting-edge DFT methodologies for 2.5D/3D multi-stacked die packaging. You will ensure comprehensive test coverage across die-to-die interfaces utilizing emerging standards like IEEE 1838.
• Analog Macro DFT: Work at the interface of digital and analog design to facilitate the integration and testability of custom analog mixed-signal blocks. You will develop novel test strategies for non-standard analog macros operating within the digital fabric.
• Test & PPA Optimization: Drive aggressive test coverage, test time, and yield targets while working closely with architects to influence the micro-architecture for better Power, Performance, and Area (PPA).
• Sign-off & Verification: Own the final DFT sign-off process. This includes Automatic Test Pattern Generation (ATPG), test vector validation, fault simulation, and ensuring clean timing closure during Static Timing Analysis (STA) for all test modes.
• Methodology Development: Contribute to the development and automation of our design flow. Set best practices for testability to ensure first-pass silicon success.
• Partner Engagement: Work to evaluate potential partners that offer AI tools that could greatly improve chip design efficiency.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of industry experience in digital DFT and test architecture, with a track record of successful tapeouts on modern process nodes (7nm, 5nm, or newer preferred).
• Deep expertise in scan compression, MBIST generation, fault modeling (stuck-at, transition, path delay), and ATPG.
• Deep understanding of physical design challenges in advanced nodes (multi-patterning, finFET effects, low-voltage operation) and their impact on test reliability.
• Expertise in Static Timing Analysis (STA) and timing closure for complex designs in shift and capture test modes.
• Expert-level mastery of standard EDA CAD tool suites for DFT implementation and vector generation.
• Strong scripting skills in Tcl, Python, or Perl to automate design flows and data analysis.
• Excellent written and verbal communication skills, with experience managing deliverables from external vendors or design houses.

Preferred Qualifications (Nice to Have)

• Hands-on experience with modern die-to-die (D2D) interconnect test strategies, chiplet testing, and 3D-IC DFT architectures.
• Experience with test architecture for Machine Learning accelerators or large-scale systolic arrays.
• Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements.
• Familiarity with state of the art AI tools to accelerate chip design.